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Features
* Utilizes the AVR(R) RISC Architecture * AVR - High-performance and Low-power RISC Architecture
- 89 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General-purpose Working Registers - Up to 12 MIPS Throughput at 12 MHz Data and Nonvolatile Program Memory - 1K Byte of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles - 64 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - Programming Lock for Flash Program and EEPROM Data Security Peripheral Features - One 8-bit Timer/Counter with Separate Prescaler - On-chip Analog Comparator - Programmable Watchdog Timer with On-chip Oscillator - SPI Serial Interface for In-System Programming Special Microcontroller Features - Low-power Idle and Power-down Modes - External and Internal Interrupt Sources - Selectable On-chip RC Oscillator for Zero External Components Specifications - Low-power, High-speed CMOS Process Technology - Fully Static Operation Power Consumption at 4 MHz, 3V, 25C - Active: 2.0 mA - Idle Mode: 0.4 mA - Power-down Mode: <1 A I/O and Packages - 15 Programmable I/O Lines - 20-pin PDIP, SOIC and SSOP Operating Voltages - 2.7 - 6.0V (AT90S1200-4) - 4.0 - 6.0V (AT90S1200-12) Speed Grades - 0 - 4 MHz, (AT90S1200-4) - 0 - 12 MHz, (AT90S1200-12)
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8-bit Microcontroller with 1K Byte of In-System Programmable Flash AT90S1200 Summary
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Description
The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the (continued)
Pin Configuration
Rev. 0838FS-10/00
Note: This is a summary document. A complete document is available on our web site at www.atmel.com.
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AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with the 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
Block Diagram
Figure 1. The AT90S1200 Block Diagram
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AT90S1200
AT90S1200
The architecture supports high-level languages efficiently as well as extremely dense assembler code programs. The AT90S1200 provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 15 generalpurpose I/O lines, 32 general-purpose working registers, internal and external interrupts, programmable Watchdog Timer with internal oscillator, an SPI serial port for program downloading and two software selectable power-saving modes. The Idle Mode stops the CPU while allowing the registers, timer/counter, watchdog and interrupt system to continue functioning. The Power-down Mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. The device is manufactured using Atmel's high-density nonvolatile memory technology. The on-chip In-System Programmable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S1200 is a powerful microcontroller that provides a highly flexible and costeffective solution to many embedded control applications. The AT90S1200 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Pin Descriptions
VCC Supply voltage pin. GND Ground pin. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip analog comparator. The Port B output buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port D (PD6..PD0) Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active. RESET Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier.
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Architectural Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. Figure 2. The AT90S1200 AVR Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 2 shows the AT90S1200 AVR Enhanced RISC microcontroller architecture. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data memories. The program memory is accessed with a 2-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Programmable Flash memory. With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subroutines and interrupts. The I/O memory space contains 64 addresses for CPU peripheral functions such as control registers, timer/counters, A/D converters and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. 4
AT90S1200
AT90S1200
AT90S1200 Register Summary
Address $3F $3E $3D $3C $3B $3A $39 $38 $37 $36 $35 $34 $33 $32 $31 $30 $2F $2E $2D $2C $2B $2A $29 $28 $27 $26 $25 $24 $23 $22 $21 $20 $1F $1E $1D $1C $1B $1A $19 $18 $17 $16 $15 $14 $13 $12 $11 $10 $0F ... $09 $08 ... $00 Name SREG Reserved Reserved Reserved GIMSK Reserved TIMSK TIFR Reserved Reserved MCUCR Reserved TCCR0 TCNT0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB Reserved Reserved Reserved PORTD DDRD PIND Reserved Reserved Reserved ACSR Reserved Reserved Bit 7 I Bit 6 T Bit 5 H Bit 4 S Bit 3 V Bit 2 N Bit 1 Z Bit 0 C
-
INT0 -
-
-
-
-
TOIE0 TOV0
-
-
-
SE -
SM
-
CS02
ISC01 CS01
ISC00 CS00
Timer/Counter0 (8 Bits)
-
-
-
-
WDE
WDP2
WDP1
WDP0
-
EEPROM Address Register EEPROM Data Register -
EEWE
EERE
PORTB7 DDB7 PINB7
PORTB6 DDB6 PINB6
PORTB5 DDB5 PINB5
PORTB4 DDB4 PINB4
PORTB3 DDB3 PINB3
PORTB2 DDB2 PINB2
PORTB1 DDB1 PINB1
PORTB0 DDB0 PINB0
-
PORTD6 DDD6 PIND6
PORTD5 DDD5 PIND5
PORTD4 DDD4 PIND4
PORTD3 DDD3 PIND3
PORTD2 DDD2 PIND2
PORTD1 DDD1 PIND1
PORTD0 DDD0 PIND0
ACD
-
ACO
ACI
ACIE
-
ACIS1
ACIS0
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical "1" to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a "1" back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
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Instruction Set Summary
Mnemonic Operands Description Operation Rd Rd + Rr Rd Rd + Rr + C Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * (FFh - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC PC + k + 1 PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if (P(b) = 0) PC PC + 2 or 3 if (P(b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC + k + 1 if (SREG(s) = 0) then PC PC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V = 0) then PC PC + k + 1 if (N V = 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1 Rd (Z) (Z) Rr Rd Rr Rd K Rd P P Rr Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None I None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None # Clocks 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1 1 ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry Two Registers SBCI Rd, K Subtract with Carry Constant from Reg. AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One's Complement NEG Rd Two's Complement SBR Rd, K Set Bit(s) in Register CBR Rd, K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register BRANCH INSTRUCTIONS RJMP k Relative Jump RCALL k Relative Subroutine Call RET Subroutine Return RETI Interrupt Return CPSE Rd, Rr Compare, Skip if Equal CP Rd, Rr Compare CPC Rd, Rr Compare with Carry CPI Rd, K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less than Zero, Signed BRHS k Branch if Half-carry Flag Set BRHC k Branch if Half-carry Flag Cleared BRTS k Branch if T-Flag Set BRTC k Branch if T-Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled DATA TRANSFER INSTRUCTIONS LD Rd, Z Load Register Indirect ST Z, Rr Store Register Indirect MOV Rd, Rr Move between Registers LDI Rd, K Load Immediate IN Rd, P In Port OUT P, Rr Out Port
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AT90S1200
AT90S1200
Instruction Set Summary (Continued)
Mnemonic Operands Description Operation I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) C,Rd(n+1) Rd(n),C Rd(7) Rd(7) C,Rd(n) Rd(n+1),C Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N 1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T 1 T 0 H1 H0 (see specific descr. for Sleep function) (see specific descr. for WDR/timer) Flags None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None # Clocks 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 BIT AND BIT-TEST INSTRUCTIONS SBI P, b Set Bit in I/O Register CBI P, b Clear Bit in I/O Register LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left through Carry ROR Rd Rotate Right through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear BST Rr, b Bit Store from Register to T BLD Rd, b Bit Load from T to Register SEC Set Carry CLC Clear Carry SEN Set Negative Flag CLN Clear Negative Flag SEZ Set Zero Flag CLZ Clear Zero Flag SEI Global Interrupt Enable CLI Global Interrupt Disable SES Set Signed Test Flag CLS Clear Signed Test Flag SEV Set Two's Complement Overflow CLV Clear Two's Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half-carry Flag in SREG CLH Clear Half-carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset
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Ordering Information(1)
Speed (MHz) 4 Power Supply 2.7 - 6.0V Ordering Code AT90S1200-4PC AT90S1200-4SC AT90S1200-4YC AT90S1200-4PI AT90S1200-4SI AT90S1200-4YI 12 4.0 - 6.0V AT90S1200-12PC AT90S1200-12SC AT90S1200-12YC AT90S1200-12PI AT90S1200-12SI AT90S1200-12YI Note: Package 20P3 20S 20Y 20P3 20S 20Y 20P3 20S 20Y 20P3 20S 20Y Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
1. Order AT90S1200A-XXX for devices with the RCEN fuse programmed.
Package Type 20P3 20S 20Y 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 20-lead, 5.3 mm Wide, Plastic Shrink Small Outline Package (SSOP)
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AT90S1200
AT90S1200
Packaging Information
20P3, 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
1.060(26.9) .980(24.9)
0.020 (0.508) 0.013 (0.330)
20S, 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters)
PIN 1
.280(7.11) .240(6.10)
PIN 1
0.299 (7.60) 0.420 (10.7) 0.291 (7.39) 0.393 (9.98)
.900(22.86) REF .210(5.33) MAX SEATING PLANE .150(3.81) .115(2.92) .110(2.79) .090(2.29) .070(1.78) .045(1.13) .325(8.26) .300(7.62) .014(.356) .008(.203) 0 REF 15
.090(2.29) MAX .005(.127) MIN
.050 (1.27) BSC
.015(.381) MIN .022(.559) .014(.356)
0.513 (13.0) 0.497 (12.6)
0.105 (2.67) 0.092 (2.34)
0.012 (0.305) 0.003 (0.076)
0 REF 8
0.013 (0.330) 0.009 (0.229)
.430(10.92) MAX
0.035 (0.889) 0.015 (0.381)
20Y, 20-lead, 5.3 mm Wide, Plastic Shrink Small Outline Package (SSOP) Dimensions in Millimeters and (Inches)
0.38 (.015) 0.25 (.010)
5.38 (.212) 7.90 (.311) 5.20 (.205) 7.65 (.301) PIN 1 ID
0.65 (.0256) BSC 7.33 (.289) 7.07 (.278)
2.67 (.105) 2.34 (.092)
0.21 (.008) 0.05 (.002)
0.20 (.008) 0.09 (.004) 0 REF 8 0.95 (.037) 0.63 (.025)
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